장우영 사진

장우영 | 공과대학 전자전기공학부

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소개

Wooyoung Jang (S’08-M'11) received the B.E. degree in radio science and technology from Kyunghee University, South Korea, in 1998, the M.S. degree in electrical and computer engineering from Yonsei University, South Korea in 2000 and the Ph.D. degree in electrical and computer engineering from the University of Texas at Austin, USA in 2011.

From 2000 to 2013, he was with the System LSI Division, Samsung Electronics, as a Senior Engineer. He is currently an Associate Professor with the Department of Electronics and Electrical Engineering, Dankook University. He has published more than 37 papers in highly referred conferences and journals, and holds four U.S. patents. His current research interests include interconnection networks, computer architecture, low-power SoC design, and machine learning.

He has served in the Technical Program Committee for the IEEE International Conference on Computer-Aided Design (ICCAD), the Technical Program Committee of IEEE International Conference on Computer Design (ICCD), the International Symposium on VLSI Design, Automation and Test (VLSI-DAT), and the International Program Committee of International Conference on Computer-Aided Design and Computer Graphics (CAD/Graphics). He has also served as a reviewer in premier journals and conferences, including IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), IEEE Transactions on Very Large Scale Integration Systems (TVLSI), IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), ACM Transactions on Design Automation of Electronic Systems (TODAES), ACM/IEEE Design Automation Conference (DAC), IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Asian and South Pacific Design Automation Conference (ASPDAC), among others.

학력

  • [1998] 학사 경희대학교 전파공학과
  • [2000] 석사 연세대학교 전기및컴퓨터공학과
  • [2011] 박사 Univ. of Texas at Austin 전기및컴퓨터공학과 SoC 구조/설계 자동화

주요경력

  • 삼성전자 (2000-02-14)

컨설팅 가능 분야

저전력 SoC 설계
고성능 컴퓨터 시스템
멀티미디어 시스템
인공지능 시스템(기계학습)

연구업적

  • 일반논문[20191001] Unaligned Burst-Aware Memory Subsystem
  • 일반논문[20190911] Adaptive Linear Address Map for Bank Interleaving in DRAMs
  • 일반논문[20181219] Screen Orientation Aware DRAM Architecture for Mobile Video and Graphic Applications
  • 일반논문[20181031] 모바일 시스템을 위한 CNN 딥 러닝 가속화 알고리즘
  • 일반논문[20181031] DRAM의 성능 향상을 위한 Pre-Refresh 기법
  • 일반논문[20171231] 병렬 TLC STT-MRAM 기반 대용량 LLC 설계
  • 일반논문[20170610] Enhancing lifetime of phase-change memory for video processor
  • 일반논문[20170601] WARP: Memory Subsystem Effective for Wrapping Bursts of a Cache
  • 일반논문[20170105] Multi-level cell STT-RAM controller for multimedia applications
  • 일반논문[20141016] Error-Correcting Code Aware Memory Subsystem
  • 일반논문[20140911] DECO: DIMM controller efficient for ECC operations
  • 일반논문[20130601] Chemical-Mechanical Polishing-Aware Application-Specific 3D NoC Design
  • 일반논문[20120801] UNISM: Unified Scheduling and Mapping for General Networks on Chip
  • 일반논문[20120601] A3MAP: Architecture-Aware Analytic Mapping for Networks-on-Chip
  • 일반논문[20111001] Application-Aware NoC Design for Efficient SDRAM Access
  • 일반논문[20110901] A voltage-frequency island aware energy optimization framework for networks-on-chip
  • 일반논문[20101001] An SDRAM-Aware Router for Networks-on-Chip
  • 저서/역서[20140730] Floyd의 디지털 논리회로
  • 지식재산권[20190507] 병렬 TLC STT MRAM 기반 대용량 LLC 및 이의 동작 제어 방법(Large scale Last level Cache based on parallel TLC STT MRAM and Method for controlling function the same)
  • 지식재산권[20170511] 연속인 가로열과 세로열의 데이터를 제공하는 동적 메모리(DRAM FOR PROVIDING SUCCESSIVE ROW AND COLUMN DATA)
  • 지식재산권[20170502] 메모리 제어 장치 및 방법(APPARATUS FOR CONTROLING MEMORY AND METHOD THEREOF)
  • 지식재산권[20120619] Apparatus and method for detecting letter box, and MPEG decoding device having the same
  • 지식재산권[20110104] System and method of decoding dual video signals
  • 지식재산권[20070626] Method and apparatus for coding digital video signal based on grouped zerotree wavelet image coding algorithm
  • 지식재산권[20050816] Apparatus and method for image coding using tree-structured quantization based on wavelet transform
  • 학술발표[20151020] FDRAM: DRAM Architecture Flexible in Successive Row and Column Accesses
  • 학술발표[20111107] Chemical-mechanical polishing aware application-specific 3D NoC design,
  • 학술발표[20100621] Voltage and frequency island optimizations for many-core/NoC designs
  • 학술발표[20100613] Application-aware NoC design for efficient SDRAM access
  • 학술발표[20100118] A3MAP: Architecture-Aware Analytic Mapping for Networks-on-Chip
  • 학술발표[20090726] An SDRAM-aware router for networks-on-chip
  • 학술발표[20081110] A voltage-frequency island aware energy optimization framework for networks-on-chip
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